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# Fast compensative design approach for the approximate squaring function

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File Name: Fast compensative design approach for the approximate squaring function

File Submitter: bogdan

File Submitted: 9 Apr 2008

File Category: IEEE papers

Fast compensative design approach for the approximate squaring function

ISSUE: IEEE Journal of Solid-State Circuits, vol. 37, pp. 95 - 97, January 2002

AUTHORS: Ming-Hwa Sheu and Su-Hon Lin

KEYWORDS: CMOS logic circuits; Combinational circuits; Error analysis; Integrated circuit design; Integrated circuit testing; Logic design; Logic testing

BIBLIOGRAPHIC ENTRY:

M. Sheu and S. Lin, "Fast compensative design approach for the approximate squaring function," IEEE Journal of Solid-State Circuits, vol. 37, pp. 95 - 97, January 2002.

ABSTRACT:

In this paper, a systematic compensation approach is presented to efficiently design the approximate squaring function with a simple combinational logic circuit. Also, a set of recursive Boolean equations for general outputs is derived such that the logic circuit can be rapidly designed and reused for various bit-width inputs. In logic implementation, our design approach possesses less circuit cost and lower critical delay. Moreover, in error analysis, the maximum relative error (MRE) and average relative error (ARE) of squaring approximation are significantly improved by at least 26.95% and 61.59%, respectively, as compared with the existing approaches. Finally, a 7-bit approximate squaring function chip is accomplished to verify the circuit performance based on 0.6-\mum CMOS technology. The chip layout occupies $127 \times 135\;\mu$ m $^{2}$ and the total number of transistors is 186.

REFERENCES:

The links below are references to articles within the collection. Please refer to the paper itself for a full list of references.

[2] Mohammad R. Soleymani, Salvatore D. Morgera; A Fast MMSE Encoding Technique for Vector Quantization, IEEE Trans. Communications, vol. COM-37, pp. 656 - 659, June 1989.

[3] Y. Ephraim; Statistical-model-based speech enhancement systems, Proc. IEEE, vol. 80, no. 10, pp. 152 - 155, Oct. 1992.

[4] K. Hwang; Computer Arithmetic: Principle, Architecture, and Design, Wiley, New York, 1979.

[5] M. Shammanna, S. Whitaker, J. Canaris; Cellular logic array for computation of squares, 3rd NASA Symp. on VLSI Design, pp. 2.4.1 - 2.4.7, 1991.

[6] Aria Eshraghi, Terri S. Fiez, Kel D. Winters, Thomas R. Fischer; Design of a new squaring function for the Viterbi algorithm, IEEE Journal of Solid-State Circuits, vol. 29, pp. 1102 - 1107, September 1994.

[7] Ahmed A. Hiasat, Hoda S. Abdel-Aty-Zohdy; Combinational logic approach for implementing an improved approximate squaring function, IEEE Journal of Solid-State Circuits, vol. 34, pp. 236 - 240, February 1999.

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