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# Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques

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File Name: Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques

File Submitter: bogdan

File Submitted: 9 Apr 2008

File Category: Ieee papers

Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques

ISSUE: IEEE Journal of Solid-State Circuits, vol. 37, pp. 63 - 76, January 2002

AUTHORS: Chung-Hsun Huang, Jinn-Shyan Wang, and Yan-Chao Huang

KEYWORDS: A/D converters; Analog-to-digital conversion (ADC); CMOS logic circuits; CMOSFET logic devices; Encoding; Logic circuits; Logic design; Low-power electronics; Multivalued logic circuits; Protocols; Very-high-speed integrated circuits

BIBLIOGRAPHIC ENTRY:

C. Huang, J. Wang, and Y. Huang, "Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques," IEEE Journal of Solid-State Circuits, vol. 37, pp. 63 - 76, January 2002.

ABSTRACT:

Lookahead signals to form the multilevel folding architecture for priority-encoding-based designs was used to improve the performance to the order of $O (\log N)$ . Analysis showed that both the multilevel lookahead and the multilevel folding techniques could be easily merged and implemented in the dynamic CMOS circuits. For the 256-bit priority encoder, the new design adopting all the proposed techniques can achieve nearly ten times performance while spending nearly half the power consumption as compared to the conventional design, utilizing only a simple lookahead structure. For the 64-bit incrementer/decrementer, the new design adopting all the proposed techniques requires less than one-third delay time as compared to a high-speed carry-select adder (CSA)-based incrementer/decrementer. The power consumption evaluated at the maximum operating frequency and the transistor count of the new incrementer/decrementer are also reduced to 67% and 35%, respectively, as compared to the CSA-based design. The measurement results indicate that the proposed 256-bit priority encoder and the proposed 64-bit incrementer/decrementer can operate up to 116 and 139 MHz, respectively, when they are designed based on a 0.6-\mum CMOS technology.

REFERENCES:

[1] D. H. Summerville, J. G. Delgado-Frias, S. Vassiliadis; A flexible bit-pattern associative router for interconnection networks, IEEE Trans. Parallel Distrib. Syst., vol. 7, pp. 477 - 485, May 1996.

[2] Hiroshi Kadota, Jiro Miyake, Yoshito Nishimichi, Hitoshi Kudoh, Keiichi Kagawa; An 8-kbit content-addressable and Reentrant memory, IEEE Journal of Solid-State Circuits, vol. 20, pp. 951 - 957, October 1985.

[4] R. Hashemian; Highly parallel increment/decrement using CMOS technology, Proc. 33rd IEEE Midwest Symp. Circuit and Systems, vol. 2, pp. 866 - 869, 1991.

[5] C.-H. Huang, J.-S. Wang, Y.-C. Huang; A high-speed CMOS incrementer/decrementer, Proc. IEEE Int. Symp. Circuit and Systems, vol. 4, pp. 88 - 91, May 2001.

[6] José Delgado-Frias, Jabulani Nyathi; A high-performance encoder with priority lookahead, IEEE Trans. Circuit Syst. I, vol. CAS-47, pp. 1390 - 1393, September 2000.

[7] Jinn-Shyan Wang, Chung-Hsun Huang; High-speed and low-power CMOS priority encoders, IEEE Journal of Solid-State Circuits, vol. 35, pp. 1511 - 1514, October 2000.

[8] 0.6-$\mu$m CMOS ASIC Process Dig., Taiwan Semiconductor Manufacturing Corporation, 1996.

[9] N. West, K. Eshraghian; Principles of CMOS VLSI Design, Addison-Wesley, Reading, MA, ch. 8, 1993.

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