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Guest Ignas

Need some help with Verilog design

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Guest Ignas

Hi there.

Situation: I am using a counter to move to the next state with every posedge of the clk:

always @(posedge clk)

state <= state + 1;

In addition, with every posedge of the clk I also have a new word (dataIn) of 8 bits. And if this new word exceeds my limit, I want to remain in particular state, for example, for 5 clock cycles. So, in this case I need somehow to stop counter for 5 clock cycles, so that state wouldn't change, but I can't imagine how to do this. Or, I have another idea to use the other counter to keep track of long I should remain in this state.. So I'm very confused, which idea is better, or which idea is easier to design...any help would be appreciated..

By the way, here is some of my code:

always @(posedge clk)

begin

checkpoint <= dataIn;

if (signal_limit <= checkpoint)

begin : signal_copy

repeat (4)

begin

state <= state;

end

P.S. I'm newbie in verilog

Regards,

Ignas

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Guest Sutej

Hi Ignas,

You can write like this(Simple Way)

assign checkpoint = dataIn;

always@ (posedge clk) begin

if(signal_limit <= checkpoint) begin

if(Count <= 4)

Count <= 0;

else

Count <= Count + 1 ;

end

else

State <= State + 1;

end

Hi there.

Situation: I am using a counter to move to the next state with every posedge of the clk:

always @(posedge clk)

state <= state + 1;

In addition, with every posedge of the clk I also have a new word (dataIn) of 8 bits. And if this new word exceeds my limit, I want to remain in particular state, for example, for 5 clock cycles. So, in this case I need somehow to stop counter for 5 clock cycles, so that state wouldn't change, but I can't imagine how to do this. Or, I have another idea to use the other counter to keep track of long I should remain in this state.. So I'm very confused, which idea is better, or which idea is easier to design...any help would be appreciated..

By the way, here is some of my code:

always @(posedge clk)

begin

checkpoint <= dataIn;

if (signal_limit <= checkpoint)

begin : signal_copy

repeat (4)

begin

state <= state;

end

P.S. I'm newbie in verilog

Regards,

Ignas

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