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  1. A 5-mW Sigma--Delta modulator with 84-dB dynamic range for GSM/EDGE by Omid Oliaei, Patrick Clément, and Philippe Gorisse

    A 5-mW Sigma--Delta modulator with 84-dB dynamic range for GSM/EDGE
    ISSUE: IEEE Journal of Solid-State Circuits, vol. 37, pp. 2 - 10, January 2002

    AUTHORS: Omid Oliaei, Patrick Clément, and Philippe Gorisse

    KEYWORDS: BiCMOS integrated circuits; Bipolar-CMOS integrated circuits; Cascade networks; Cellular radio; CMOS integrated circuits; Integrated circuit design; Low-power electronics; Mobile radio systems; Sigma-delta modulation; Signal resolution; Transceivers

    BIBLIOGRAPHIC ENTRY:
    O. Oliaei, P. Clément, and P. Gorisse, "A 5-mW Sigma--Delta modulator with 84-dB dynamic range for GSM/EDGE," IEEE Journal of Solid-State Circuits, vol. 37, pp. 2 - 10, January 2002.

    ABSTRACT:

    A sigma-delta modulator designed as part of a complete GSM/EDGE transceiver is described. High-resolution wide-band analog-to-digital converters enable the receiver to rely on digital processing, rather than analog filtering, to extract the desired signal from blocking channels. High linearity and low power consumption are the most stringent requirements for the converters in this wireless application. A single-bit 2-2-cascaded modulator operating at 13 MHz has been adopted for high linearity and stability. Low-power low-voltage techniques have been applied along with a top-down design approach in order to minimize the power dissipation. The $\Sigma \Delta$ modulator achieves 13.5bits of resolution over a bandwidth of 180 kHz while dissipating 5 mW from 1.8-V and 2.4-V supplies. The circuit has been implemented in the CMOS portion of a 0.4- \mum (drawn) BiCMOS technology and occupies an active area of 0.4 mm $^{2}$ .

    REFERENCES:
    The links below are references to articles within the collection. Please refer to the paper itself for a full list of references.

    [1] Anders Furuskär, Sara Mazur, Frank Müller, Håkan Olofsson; EDGE: Enhanced data rates for GSM and TDMA/136 evolution, IEEE Personal Communications, vol. 6, pp. 56 - 66, June 1999.

    [2] Angelo Nagari, Alessandro Mecchia, Ermes Viani, Sergio Pernici, Pierangelo Confalonieri, Germano Nicollini; A 2.7-V 11.8-mW baseband ADC with 72-dB dynamic range for GSM applications, IEEE Journal of Solid-State Circuits, vol. 35, pp. 798 - 806, June 2000.

    [3] Lucien J. Breems, Eric J. van der Zwan, Johan H. Huijsing; A 1.8-mW CMOS ΣΔ modulator with integrated mixer for A/D conversion of IF signals, IEEE Journal of Solid-State Circuits, vol. 35, pp. 468 - 475, April 2000.

    [4] Thomas Burger, Qiuting Huang; A 13.5mW, 185Msample/s ΔΣ-modulator for UMTS/GSM dual-standard IF reception, IEEE International Solid-State Circuits Conference, vol. XLIV, pp. 44 - 45, February 2001.

    [5] Michiel Steyaert, Marc Borremans, Johan Janssens, Bram De Muer, Nobuyuki Itoh, Jan Craninckx, Jan Crols, Eiji Morifuji, Hisayo Sasaki Momose, Willy Sansen; A single-chip CMOS transceiver for DCS-1800 wireless communications, IEEE International Solid-State Circuits Conference, vol. XLI, pp. 48 - 49, February 1998.

    [6] Jan Crols, Michel S. J. Steyaert; A single-chip 900 MHz CMOS receiver front-end with a high performance low-IF topology, IEEE Journal of Solid-State Circuits, vol. 30, pp. 1483 - 1492, December 1995.

    [7] J. Crols, M. S. J. Steyaert; Low-IF topologies for high-performance analog front ends of fully integrated receivers, IEEE Trans. Circuit Syst. II, vol. CAS-45, pp. 269 - 282, March 1998.

    [8] F. K. Chai, C. Kyono, V. Ilderem, M. Kaneshiro, D. Zupac, S. Bigelow, C. Ramiah, P. Dahl, R. Braithwaite, D. Morgan, S. Hildreth, G. Grynkewich; A cost-effective 0.25-mm Leff BiCMOS technology featuring graded-channel CMOS (GCMOS) and a quasiself-aligned (QSA) NPN for RF wireless applications, Proc. 2000 IEEE BCTM, pp. 110 - 113.

    [9] T. G. M. Kleinpenning; On $1/f$ trapping noise in MOSTs, IEEE Trans. Electron. Dev., vol. 37, pp. 2084 - 2089, Sept. 1990.

    [10] Yves Geerts, Augusto Manuel Marques, Michel S. J. Steyaert, Willy Sansen; A 3.3-V, 15-bit, delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL applications, IEEE Journal of Solid-State Circuits, vol. 34, pp. 927 - 936, July 1999.

    [11] Louis A. Williams III, Bruce A. Wooley; A third-order sigma-delta modulator with extended dynamic range, IEEE Journal of Solid-State Circuits, vol. 29, pp. 193 - 202, March 1994.

    [12] Shahriar Rabii, Bruce A. Wooley; A 1.8-V digital-audio sigma-delta modulator in 0.8-µm CMOS, IEEE Journal of Solid-State Circuits, vol. 32, pp. 783 - 796, June 1997.

    [13] Arnold R. Feldman, Bernhard E. Boser, Paul R. Gray; A 13-bit, 1.4-MS/s sigma-delta modulator for RF baseband channel applications, IEEE Journal of Solid-State Circuits, vol. 33, pp. 1462 - 1469, October 1998.

    [14] O. Oliaei; Thermal noise analysis of multiinput SC integrators for Delta-Sigma modulator design, Proc. IEEE Int. Symp. Circuits Syst., vol. 4, pp. 425 - 428, May 2000.

    [15] Dan B. Kasha, Wai L. Lee, Axel Thomsen; A 16-mW, 120-dB linear switched-capacitor delta-sigma modulator with dynamic biasing, IEEE Journal of Solid-State Circuits, vol. 34, pp. 921 - 926, July 1999.

    [16] Feng Wang, Ramesh Harjani; Power Analysis and Optimal Design of Opamps for Oversampled Converters, IEEE Trans. Circuit Syst. II, vol. CAS-46, pp. 359 - 369, April 1999.

    [17] Howard C. Yang, David J. Allstot; Considerations for fast settling operational amplifiers, IEEE Trans. Circuit Syst., vol. CAS-37, pp. 326 - 334, March 1990.

    [18] David B. Ribner, Richard D. Baertsch, Steven L. Garverick, Donald T. McGrath, Joseph E. Krisciunas, Toshiaki Fujii; A third-order multistage sigma-delta modulator with reduced sensitivity to nonidealities, IEEE Journal of Solid-State Circuits, vol. 26, pp. 1764 - 1774, December 1991.

    [19] K. R. Laker, W. M. Sansen; Design of Analog Integrated Circuits and Systems, McGraw-Hill, New York, 1994.

    [20] Jorge Grilo, Edward MacRobbie, Raouf Halim, Gabor Temes; A 1.8V 94dB dynamic range ΣΔ modulator for voice applications, IEEE International Solid-State Circuits Conference, vol. XXXIX, pp. 230 - 231, February 1996.

    [21] B. Razavi; Principles of Data Conversion System Design, IEEE Press, New York, 1995.

    [22] B. P. Brandt; High-speed cascaded DS ADCs, Delta-Sigma Data Converters, Theory, Design and Simulation, S. R. Norsworthy, R. Scherier, G. C. Temes, Eds., IEEE Press, New York, ch. 7, 1996.

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  2. A wideband CMOS Sigma--Delta modulator with incremental data weighted averaging by Tai-Haur Kuo, Kuan-Dar Chen, and Horng-Ru Yeng

    A wideband CMOS Sigma--Delta modulator with incremental data weighted averaging

    ISSUE: IEEE Journal of Solid-State Circuits, vol. 37, pp. 11 - 17, January 2002

    AUTHORS: Tai-Haur Kuo, Kuan-Dar Chen, and Horng-Ru Yeng

    KEYWORDS: A/D and D/A converters; CMOS integrated circuits; Feedforward; High-speed integrated circuits; Integrated circuit design; Integrated circuit measurements; Integrated circuit noise; Low-power electronics; Sigma-delta modulation; Signal sampling

    BIBLIOGRAPHIC ENTRY:
    T. Kuo, K. Chen, and H. Yeng, "A wideband CMOS Sigma--Delta modulator with incremental data weighted averaging," IEEE Journal of Solid-State Circuits, vol. 37, pp. 11 - 17, January 2002.

    ABSTRACT:

    A low-complexity high-speed circuit is proposed for the implementation of an incremental data weighted averaging (IDWA) technique used for reducing digital-to-analog converter (DAC) noise due to component mismatches. IDWA can achieve very good performance even when it is used with a low oversampling ratio (OSR), which reduces demands on circuit speed and power consumption. Therefore, the IDWA is highly suitable for wideband, low-power and small-area sigma-delta modulator (SDM) implementation. Incorporating the IDWA technique, a fourth-order feedforward (FF) SDM with an OSR of 12 and a 4-bit internal quantizer is implemented with a 2.5-V 0.25-\mum CMOS process. Measurement results show that the SDM operating from a 2.5-V supply voltage can achieve respective dynamic ranges (DRs) of 84/80 dB and spurious-free dynamic ranges (SFDRs) of 90/85 dB with signal bandwidths of 1.25/2 MHz at sampling frequencies of 30/48 MHz. The power dispissation is less than 105 mW and the active area is 2.6 mm $^{2}$ . Wider bandwidth, lower OSR, less power, and lower supply voltage are achieved compared with two recently published 3.3-V/3-V CMOS wideband SDMs with comparable SNDR performance.

    REFERENCES:
    The links below are references to articles within the collection. Please refer to the paper itself for a full list of references.

    [1] Rex T. Baird, Terri S. Fiez; Linearity enhancement of multibit DeltaSigma A/D and D/A converters using data weighted averaging, IEEE Trans. Circuit Syst. II, vol. CAS-42, pp. 753 - 762, December 1995.

    [2] Russ E. Radke, Aria Eshraghi, Terri S. Fiez; A 14-bit current-mode ΣΔ DAC based upon rotated data weighted averaging, IEEE Journal of Solid-State Circuits, vol. 35, pp. 1074 - 1084, August 2000.

    [3] Ichiro Fujimori, Lorenzo Longo, Armond Hairapetian, Kazushi Seiyama, Steve Kosic, Jun Cao, Shu-Lap Chan; A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8 × oversampling ratio, IEEE Journal of Solid-State Circuits, vol. 35, pp. 1820 - 1828, December 2000.

    [4] Ian Galton; Spectral shaping of circuit errors in digital-to-analog converters, IEEE Trans. Circuit Syst. II, vol. CAS-44, pp. 808 - 817, October 1997.

    [5] Kuan-Dar Chen, Tai-Haur Kuo; An Improved Technique for Reducing Baseband Tones in Sigma-Delta Modulators Employing Data Weighted Averaging Algorithm Without Adding Dither, IEEE Trans. Circuit Syst. II, vol. CAS-46, pp. 63 - 68, January 1999.

    [6] Tai-Haur Kuo, Kuan-Dar Chen, Jhy-Rong Chen; Automatic Coefficients Design for High-Order Sigma-Delta Modulators, IEEE Trans. Circuit Syst. II, vol. CAS-46, pp. 6 - 15, January 1999.

    [7] Yves Geerts, Augusto Manuel Marques, Michel S. J. Steyaert, Willy Sansen; A 3.3-V, 15-bit, delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL applications, IEEE Journal of Solid-State Circuits, vol. 34, pp. 927 - 936, July 1999.

    [8] James Morizio, Michael Hoke, Taskin Kocak, Clark Geddie, Chris Hughes, John Perry, Srinadh Madhavapeddi, Michael H. Hood, George Lynch, Harufusa Kondoh, T. Kumamoto, Takashi Okuda, Hiroshi Noda, Masahiko Ishiwaki, Takahiro Miki, Masao Nakaya; 14-bit 2.2-MS/s sigma-delta ADC's, IEEE Journal of Solid-State Circuits, vol. 35, pp. 968 - 976, July 2000.

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  3. A CMOS highly linear channel-select filter for 3G multistandard integrated wireless receivers

    A CMOS highly linear channel-select filter for 3G multistandard integrated wireless receivers

    ISSUE: IEEE Journal of Solid-State Circuits, vol. 37, pp. 27 - 37, January 2002

    AUTHORS: Hussain A. Alzaher, Hassan O. Elwan, and Mohammed Ismail

    KEYWORDS: Butterworth filters; CMOS integrated circuits; Low-pass filters; Low-power electronics; Mobile radio; Programmable filters; Radio receivers

    BIBLIOGRAPHIC ENTRY:
    H. A. Alzaher, H. O. Elwan, and M. Ismail, "A CMOS highly linear channel-select filter for 3G multistandard integrated wireless receivers," IEEE Journal of Solid-State Circuits, vol. 37, pp. 27 - 37, January 2002.

    ABSTRACT:

    A new approach for designing digitally programmable CMOS integrated baseband filters is presented. The proposed technique provides a systematic method for designing filters exhibiting high linearity and low power. A sixth-order Butterworth low-pass filter with 14-bit bandwidth tuning range is designed for implementing the baseband channel-select filter in an integrated multistandard wireless receiver. The filter consumes a current of 2.25 mA from a 2.7-V supply and occupies an area of 1.25 mm $^2$ in a 0.5-\mum chip. The proposed filter design achieves high spurious free dynamic ranges (SFDRs) of 92 dB for PDC (IS-54), 89 dB for GSM, 84 dB for IS-95, and 80 dB for WCDMA.

    REFERENCES:

    [1] Jacques C. Rudell, Jia-Jiunn Ou, Thomas Byunghak Cho, George Chien, Francesco Brianti, Jeffrey A. Weldon, Paul R. Gray; A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applications, IEEE Journal of Solid-State Circuits, vol. 32, pp. 2071 - 2088, December 1997.

    [2] Todd L. Brooks, David H. Robertson, Daniel F. Kelly, Anthony Del Muro, Stephen W. Harston; A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR, IEEE Journal of Solid-State Circuits, vol. 32, pp. 1896 - 1906, December 1997.

    [3] Aarno Pärssinen, Jarkko Jussila, Jussi Ryynänen, Lauri Sumanen, Kari A. I. Halonen; A 2-GHz wide-band direct conversion receiver for WCDMA applications, IEEE Journal of Solid-State Circuits, vol. 34, pp. 1893 - 1903, December 1999.

    [4] Mikio Koyama, Tadashi Arai, Hiroshi Tanimoto, Yoshihiro Yoshida; A 2.5-V active low-pass filter using all-n-p-n Gilbert cells with a 1-Vp-p linear input range, IEEE Journal of Solid-State Circuits, vol. 28, pp. 1246 - 1253, December 1993.

    [5] Fuji Yang, Christian C. Enz; A low-distortion BiCMOS seventh-order Bessel filter operating at 2.5 V supply, IEEE Journal of Solid-State Circuits, vol. 31, pp. 321 - 330, March 1996.

    [6] Clemens H. J. Mensink, Bram Nauta, Hans Wallinga; A CMOS "soft-switched" transconductor and its application in gain control and filters, IEEE Journal of Solid-State Circuits, vol. 32, pp. 989 - 998, July 1997.

    [7] Derek K. Shaeffer, Arvin R. Shahani, S. S. Mohan, Hirad Samavati, Hamid R. Rategh, Maria del Mar Hershenson, Min Xu, C. Patrick Yue, Daniel J. Eddleman, Thomas H. Lee; A 115-mW, 0.5-µm CMOS GPS receiver with wide dynamic-range active filters, IEEE Journal of Solid-State Circuits, vol. 33, pp. 2219 - 2231, December 1998.

    [8] Changsik Yoo, Seung-Wook Lee, Wonchan Kim; A ±1.5-V, 4-MHz CMOS continuous-time filter with a single-integrator based tuning, IEEE Journal of Solid-State Circuits, vol. 33, pp. 18 - 27, January 1998.

    [9] Farbod Behbahani, Weeguan Tan, Ali Karimi-Sanjaani, Andreas Roithmeier, Asad A. Abidi; A broad-band tunable CMOS channel-select filter for a low-IF wireless receiver, IEEE Journal of Solid-State Circuits, vol. 35, pp. 476 - 489, April 2000.

    [10] Thomas B. Cho, George Chien, Francesco Brianti, Paul R. Gray; A power-optimized CMOS Baseband channel filter and ADC for cordless applications, Symp. VLSI Circuits Dig. 10, pp. 64 - 65, June 1996.

    [11] Paul J. Chang, Ahmadreza Rofougaran, Asad A. Abidi; A CMOS channel-select filter for a direct-conversion wireless receiver, IEEE Journal of Solid-State Circuits, vol. 32, pp. 722 - 729, May 1997.

    [12] Haideh Khorramabadi, Maurice J. Tarsia, Nam S. Woo; Baseband filters for IS-95 CDMA receiver applications featuring digital automatic frequency tuning, IEEE International Solid-State Circuits Conference, vol. XXXIX, pp. 172 - 173, February 1996.

    [13] Saska Lindfors, Jarkko Jussila, Kari Halonen, Lauri Siren; A 3-V continuous-time filter with on-chip tuning for IS-95, IEEE Journal of Solid-State Circuits, vol. 34, pp. 1150 - 1154, August 1999.

    [14] T. Hollman, S. Lindfors, M. Lansirinne, J. Jussila, K. Halonen; A 2.7V CMOS dual-mode baseband filter for PDC and WCDMA, Proc. Eur. Solid-State Circuits Conf., Stockholm, Sweden, pp. 176 - 179, Sept. 2000.

    [15] Klaas Bult, Govert J. G. M. Geelen; An inherently linear and compact MOST-only current division technique, IEEE Journal of Solid-State Circuits, vol. 27, pp. 1730 - 1735, December 1992.

    [16] Clemens M. Hammerschmied, Qiuting Huang; Design and implementation of an untrimmed MOSFET-only 10-bit A/D converter with -79-dB THD, IEEE Journal of Solid-State Circuits, vol. 33, pp. 1148 - 1157, August 1998.

    [17] H. A. Alzaher, M. Ismail; Digitally tuned analogue integrated filters using R-2R ladder, Electron. Lett., vol. 36, pp. 1278 - 1280, 2000.

    [18] R. L. Ukeiley; Digitally controlled active filters, Proc. IEEE Int. Symp. Circuits and Systems, pp. 573 - 577, 1974.

    [19] Anna M. Durham, William Redman-White, John B. Hughes; High-linearity continuous-time filter in 5-V VLSI CMOS, IEEE Journal of Solid-State Circuits, vol. 27, pp. 1270 - 1276, September 1992.

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  4. A 2.5-Mb/s GFSK 5.0-Mb/s 4-FSK Automatically calibrated Σ--Δ frequency synthesizer

    A 2.5-Mb/s GFSK 5.0-Mb/s 4-FSK Automatically calibrated Σ--Δ frequency synthesizer

    ISSUE: IEEE Journal of Solid-State Circuits, vol. 37, pp. 18 - 26, January 2002

    AUTHORS: Daniel R. McMahill and Charles G. Sodini

    KEYWORDS: BiCMOS integrated circuits; Bipolar-CMOS integrated circuits; Calibration; Circuit tuning; Compensation; Frequency synthesizers; Frequency-shift keying; Minimum-shift keying; Phase-locked loop (PLL); PLLs; Sigma-delta modulation; Signal generators; Tuning circuits; Voltage-controlled oscillator (VCO)

    BIBLIOGRAPHIC ENTRY:
    D. R. McMahill and C. G. Sodini, "A 2.5-Mb/s GFSK 5.0-Mb/s 4-FSK Automatically calibrated Σ--Δ frequency synthesizer," IEEE Journal of Solid-State Circuits, vol. 37, pp. 18 - 26, January 2002.

    ABSTRACT:

    This paper describes a new sigma-delta ( Σ-Δ) frequency synthesizer for Gaussian frequency and minimum shift keying (GFSK/GMSK) modulation. The key innovation is an automatic calibration circuit which tunes the phase-locked loop (PLL) response to compensate for process tolerance and temperature variation. The availability of this new calibration method allows the use of precompensation techniques to achieve high data rate modulation without requiring factory calibration. The calibration method can be applied to GFSK/GMSK modulation and also M-ary FSK modulation. The PLL, including 1.8-GHz voltage controlled oscillator (VCO), Σ- Δ modulator, and automatic calibration circuit, has been implemented in a 0.6-\mum BiCMOS integrated circuit. The test chip achieves 2.5 Mb/s using GFSK and 5.0 Mb/s using 4-FSK.

    REFERENCES:
    The links below are references to articles within the collection. Please refer to the paper itself for a full list of references.

    [1] H. Hayashi, M. Nakatsugawa, M. Muraguchi; Quasi-linear amplification using self phase distortion compensation technique, IEEE Trans. Microwave Theory Tech., vol. 43, pp. 2557 - 2564, Nov. 1995.

    [2] B. Miller, R. J. Conley; A multiple modulator fractional divider, IEEE Trans. Instrum. Measure., vol. 40, pp. 578 - 583, June 1991.

    [3] Thomas A.D. Riley, Miles A. Copeland; A simplified continuous phase modulator technique, IEEE Trans. Circuit Syst. II, vol. CAS-41, pp. 321 - 328, May 1994.

    [4] Michael H. Perrott, Theodore L. Tewksbury III, Charles G. Sodini; A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation, IEEE Journal of Solid-State Circuits, vol. 32, pp. 2048 - 2060, December 1997.

    [5] Daniel R. McMahill, Charles G. Sodini; Automatic calibration of modulated Σ - Δ frequency synthesizers, Symp. VLSI Circuits Dig. 15, pp. 51 - 54, June 2001.

    [6] Hikmet Sari, Saïd Moridi; New Phase and Frequency Detectors for Carrier Recovery in PSK and QAM Systems, IEEE Trans. Communications, vol. COM-36, pp. 1035 - 1043, September 1988.

    [7] F. M. Gardner; Phaselock Techniques, Wiley, New York, 1979.

    [8] Tsuneo Tsukahara, Masayuki Ishikawa, Masahiro Muraguchi; A 2-V 2-GHz Si-bipolar direct-conversion quadrature modulator, IEEE Journal of Solid-State Circuits, vol. 31, pp. 263 - 267, February 1996.

    [9] Wolfgang Heimsch, Birgit Hoffmann, Roland Krebs, Ernst Müllner, Bruno Pfäffel, Klaus Ziemann; Merged CMOS/bipolar current switch logic (MCSL), IEEE Journal of Solid-State Circuits, vol. 24, pp. 1307 - 1311, October 1989.

    [10] Hooman Reyhani, Philip Quinlan; A 5 V, 6-b, 80 Ms/s BiCMOS flash ADC, IEEE Journal of Solid-State Circuits, vol. 29, pp. 873 - 878, August 1994.

    [11] B. Sklar, f. harris; Advanced communications systems using digital signal processing, UCLA Course Notes, Engineering 881.123, Univ. of California, Los Angeles, July 1995.

    [12] Anantha P. Chandrakasan, Samuel Sheng, Robert W. Brodersen; Low-power CMOS digital design, IEEE Journal of Solid-State Circuits, vol. 27, pp. 473 - 484, April 1992.

    [13] R. E. Crochiere, L. R. Rabiner; Multirate Digital Signal Processing, Prentice-Hall, Englewood Cliffs, NJ, 1983.

    [14] Eugene B. Hogenauer; An economical class of digital filters for decimation and interpolation, IEEE Trans. Acoust., Speech, Signal Processing, vol. 29, pp. 155 - 162, April 1981.

    [15] Henry Samueli; An improved search algorithm for the design of multiplierless FIR filters with powers-of-two coefficients, IEEE Trans. Circuit Syst., vol. CAS-36, pp. 1044 - 1047, July 1989.

    [16] A. Oppenheim, R. Schafer; Discrete-Time Signal Processing, Prentice-Hall, Englewood Cliffs, NJ, 1989.

    [17] Richard I. Hartley; Subexpression sharing in filters using canonic signed digit multipliers, IEEE Trans. Circuit Syst. II, vol. CAS-43, pp. 677 - 688, October 1996.

    [18] D. Hitko, T. Tewksbury, C. Sodini; A 1 V, 5 mW, 1.8 GHz, balanced voltage-controlled oscillator with an integrated resonator, Int. Symp. Low Power Electronics and Design Proceedings, pp. 46 - 51, Aug. 1997.

    [19] Kuniharu Uchimura, Toshio Hayashi, Tadakatsu Kimura, Atsushi Iwata; Oversampling A-to-D and D-to-A converters with multistage noise shaping modulators, IEEE Trans. Acoust., Speech, Signal Processing, vol. 36, pp. 1899 - 1905, December 1988.

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  5. Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1 : 8 DEMUX

    Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1 : 8 DEMUX

    ISSUE: IEEE Journal of Solid-State Circuits, vol. 37, pp. 38 - 50, January 2002

    AUTHORS: Keiji Kishine, Kiyoshi Ishii, and Haruhiko Ichino

    KEYWORDS: Bipolar integrated circuits; Circuit optimization; Demultiplexing equipment; Jitter; Low-power electronics; Optical receivers; Phase-locked loop (PLL); PLLs; Wide-area network (WAN)

    BIBLIOGRAPHIC ENTRY:
    K. Kishine, K. Ishii, and H. Ichino, "Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1 : 8 DEMUX," IEEE Journal of Solid-State Circuits, vol. 37, pp. 38 - 50, January 2002.

    ABSTRACT:

    A loop parameter optimization method for a phase-locked loop (PLL) used in wide area networks (WANs) is proposed as a technique for achieving good jitter characteristics. It is shown that the jitter characteristics of the PLL, especially jitter transfer and jitter generation, depend strongly on the key parameter $\zeta \omega_{n}$ ( $\zeta$ is a damping factor and \omegan is the natural angular frequency of the PLL), and that the optimization focusing on the $\zeta \omega_{n}$ dependence of the jitter characteristics make it possible to comprehensively determine loop parameters and loop filter constants for a PLL that will fully comply with ITU-T jitter specifications. Using the optimization method with the low-jitter circuit design technique, a low-jitter and low-power 2.5-Gb/s optical receiver IC integrated with a limiting amplifier, clock and data recovery (CDR), and demultiplexer (DEMUX) is fabricated using 0.5-\mu m Si bipolar technology ( $f_{T}=40$ GHz). The jitter characteristics of the IC meet all three types of jitter specifications given in ITU-T recommendation G.783. In particular, the measured jitter generation is 3.2 ps rms, which is lower than that of an IC integrated with only a CDR in our previous work. In addition, the pull-in range of the PLL is 50 MHz and the power consumption of the IC is only 0.68 W (limiting amplifier: 0.2 W, CDR (PLL): 0.3 W, DEMUX: 0.18 W) at a supply voltage of $-$ 3.3 V and only 0.35 W at a supply voltage of $-$ 2.5 V (without output buffers).

    REFERENCES:

    [1] Digital line systems based on the synchronous digital hierarchy for use on optical fiber cables, ITU-T Recommendation G.783, International Telecommunication Union.

    [2] Akira Tanabe, Masayuki Soda, Yasushi Nakahara, Akio Furukawa, Takao Tamura, Kazuyoshi Yoshida; A single chip 2.4 Gb/s CMOS optical receiver IC with low substrate crosstalk preamplifier, IEEE International Solid-State Circuits Conference, vol. XLI, pp. 304 - 305, February 1998.

    [3] F. Satoet al.; A 2.4 Gb/s receiver and a 1 : 16 demultiplexer in one chip, Proc. Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), pp. 162 - 165, 1996.

    [4] Keiji Kishine, Noboru Ishihara, Ken-ichi Takiguchi, Haruhiko Ichino; A 2.5-Gb/s clock and data recovery IC with tunable jitter characteristics for use in LAN's and WAN's, IEEE Journal of Solid-State Circuits, vol. 34, pp. 805 - 812, June 1999.

    [5] K. Kishineet al.; A low-jitter, low-power 2.5-Gb/s one-chip optical receiver IC with 1 : 8 DEMUX, Proc. Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), pp. 177 - 180, 1999.

    [6] A. J. Viterbi; Principles of Coherent Communication, McGraw-Hill, New York, ch. 2, 1966.

    [7] A. Blanchard; Phase-Locked Loops, Wiley, New York, ch. 7-8, 1976.

    [8] Y. Greshichev, P. Schvan; SiGe clock and data recovery IC with liner type PLL for 10 Gb/s SONET application, Proc. Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), pp. 169 - 172, Sept. 1999.

    [9] F. M. Gardner; Phaselock Techniques, Wiley, New York, ch. 4, 1979.

    [10] Keiko Makie-Fukuda, Takafumi Kikuchi, Masao Hotta; Measurement of digital noise in mixed-signal integrated circuits, Symp. VLSI Circuits Dig. 7, pp. 23 - 24, May 1993.

    [11] M. Hiroseet al.; Low-power 2.5-Gb/s Si-bipolar IC chipset for optical receivers and transmitters using low-voltage and adjustment-free circuit techniques, IEICE Trans. Electron., vol. E82-C, no. 3, Mar. 1999.

    [12] Noboru Ishihara, Yukio Akazawa; A monolithic 156 Mb/s clock and data recovery PLL circuit using the sample-and-hold technique, IEEE Journal of Solid-State Circuits, vol. 29, pp. 1566 - 1571, December 1994.

    [13] R. G. Swartz; Ultra-high speed multiplexer/demultiplexer architectures, J. High Speed Electron., vol. 1, pp. 73 - 99, 1990.

    [14] Kenji Kawai, Keiichi Koike, Yuichiro Takei, Akira Onozawa, Hitoshi Obara, Haruhiko Ichino; A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSI chip using low-power bipolar-LSI design, IEEE Journal of Solid-State Circuits, vol. 34, pp. 12 - 17, January 1999.

    [15] Marc J. Loinaz, David K. Su, Bruce A. Wooley; Experimental results and modeling techniques for switching noise in mixed-signal integrated circuits, Symp. VLSI Circuits Dig. 6, pp. 40 - 41, June 1992.

    [16] C. Yamaguchiet al.; A 0.5-$\mu$m bipolar technology using a new base formation method, Proc. Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), pp. 63 - 66, 1993.

    Mozhgan Mansuri, Chih-Kong Ken Yang; Jitter optimization based on phase-locked loop design parameters, IEEE Journal of Solid-State Circuits, vol. 37, pp. 1375 - 1382, November 2002.

    10 downloads

    Submitted

  6. A power-efficient wide-range phase-locked loop by Oscal T.-C. Chen and Robin Ruey-Bin Sheen

    A power-efficient wide-range phase-locked loop

    ISSUE: IEEE Journal of Solid-State Circuits, vol. 37, pp. 51 - 62, January 2002

    AUTHORS: Oscal T.-C. Chen and Robin Ruey-Bin Sheen

    KEYWORDS: Clocks; CMOS integrated circuits; Low-power electronics; Modulators, demodulators, discriminators and mixers; Phase-locked loop (PLL); PLLs; Programmable circuits; Voltage-controlled oscillator (VCO)

    BIBLIOGRAPHIC ENTRY:
    O. T. Chen and R. R. Sheen, "A power-efficient wide-range phase-locked loop," IEEE Journal of Solid-State Circuits, vol. 37, pp. 51 - 62, January 2002.

    ABSTRACT:

    This work presents a phase-locked loop for clock generation that consists of a phase/frequency detector, charge pump, loop filter, range-programmable voltage-controlled ring oscillator, and programmable divider. The phase/frequency detector and charge pump are designed to reduce the dead zone and charge sharing for enhancing the locking performance, respectively. In the design of the range-programmable voltage-controlled oscillator, the original inverter ring of a delay line is divided into several smaller ones, and then they are recombined in parallel to each other. Programming the number of paralleled inverter rings allows us to generate the wide-range clock frequencies. This design shuts off some inverters that are not in use to reduce power consumption. To allow the phase-locked loop to shut off inverters, the feasibility of using controllable inverters by the output-switch and power-switch schemes is explored. Theoretical analyses indicate that power consumption of the voltage-controlled oscillator depends on transistors' sizes rather than operating frequencies. By applying the TSMC 0.35-\mum CMOS technology, the proposed phase-locked loop that uses the power-switch scheme can yield clock signals ranging from 103 MHz to 1.02 GHz at a supply voltage of 1.8 V. Moreover, power dissipation that is proportional to the number of paralleled inverter rings is measured with 1.32 to 4.59 mW. The phase-locked loop proposed herein can be used in various digital systems, providing power-efficient and wide-range clock signals for task-oriented computations.

    REFERENCES:

    [1] W.-K. Chen; The VLSI Handbook, IEEE Press, New York, 2000.

    [2] B. Razavi; Monolithic Phase-Locked Loops and Clock Recovery Circuits, IEEE Press, New York, 1996.

    [3] A. Chandrakasan, R. Brodersen; Low-Power CMOS Design, IEEE Press, New York, 1998.

    [4] Ian A. Young, Jeffrey K. Greason, Keng L. Wong; A PLL clock generator with 5 to 10 MHz of lock range for microprocessors, IEEE Journal of Solid-State Circuits, vol. 27, pp. 1599 - 1607, November 1992.

    [5] Vincent von Kaenel, Daniel Aebischer, Christian Piguet, Evert Dijkstra; A 320 MHz, 1.5 mW @ 1.35 V CMOS PLL for microprocessor clock generation, IEEE Journal of Solid-State Circuits, vol. 31, pp. 1715 - 1722, November 1996.

    [6] W. Rhee; Design of low-jitter 1-GHz phase-locked loops for digital clock generation, Proc. IEEE Int. Symp. Circuits and Systems, pp. 520 - 523, 1999.

    [7] Patrik Larsson; A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability, IEEE Journal of Solid-State Circuits, vol. 34, pp. 1951 - 1960, December 1999.

    [8] Y. Savaria, D. Chtchvyrkov, J. Currie; A fast CMOS voltage-controlled ring oscillator, Proc. IEEE Int. Symp. Circuits and Systems, pp. 359 - 362, 1994.

    [9] Akira Matsuzawa; Low-voltage and low-power circuit design for mixed analog/digital systems in portable equipment, IEEE Journal of Solid-State Circuits, vol. 29, pp. 470 - 480, April 1994.

    [10] R.-B. Sheen, O. T.-C. Chen; A 3.3V 600MHz-1.30GHz CMOS phase-locked loop for clock synchronization of optical chip-to-chip interconnects, Proc. IEEE Int. Symp. Circuits and Systems, vol. 4, pp. 429 - 432, June 1998.

    [11] H.-J. Sung, K.-S. Yoon, H.-K. Min; A 3.3 V high speed CMOS PLL with 3-250 MHz input locking range, Proc. IEEE Int. Symp. Circuits and Systems, vol. 2, pp. 553 - 556, June 1999.

    [12] R.-B. Sheen, O. T.-C. Chen; A wide-range phase-locked loop using a range-programmable voltage-controlled oscillator, Proc. IEEE 43th Midwest Symp. Circuits and Systems, vol. 1, pp. 526 - 529, Aug. 2000.

    [13] W. Rhee; A low power, wide linear-range CMOS voltage-controlled oscillator, Proc. IEEE Int. Symp. Circuits and Systems, vol. 2, pp. 85 - 88, June 1998.

    [14] H. Sutoh, K. Yamakoshi, M. Ino; A 0.25$\mu$m CMOS/SIMOX PLL clock generator embedded in a gate array LSI with 5 to 400 MHz lock range, Proc. IEEE Custom Integrated Circuits Conf., pp. 41 - 44, 1997.

    [15] Jose Alvarez, Hector Sanchez, Gianfranco Gerosa, Roger Countryman; A wide-bandwidth low-voltage PLL for PowerPCTM microprocessors, IEEE Journal of Solid-State Circuits, vol. 30, pp. 383 - 391, April 1995.

    [16] N. Weste, K. Eshraghian; Principle of CMOS VLSI Design: A Systems Perspective, Addison-Wesley, Boston, MA, 1993.

    [17] D. Rosemarine; Accurately calculate PLL charge pump filter parameters, Microwaves & RF, pp. 89 - 94, Feb. 1999.

    13 downloads

    Submitted

  7. Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques

    Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques

    ISSUE: IEEE Journal of Solid-State Circuits, vol. 37, pp. 63 - 76, January 2002

    AUTHORS: Chung-Hsun Huang, Jinn-Shyan Wang, and Yan-Chao Huang

    KEYWORDS: A/D converters; Analog-to-digital conversion (ADC); CMOS logic circuits; CMOSFET logic devices; Encoding; Logic circuits; Logic design; Low-power electronics; Multivalued logic circuits; Protocols; Very-high-speed integrated circuits

    BIBLIOGRAPHIC ENTRY:
    C. Huang, J. Wang, and Y. Huang, "Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques," IEEE Journal of Solid-State Circuits, vol. 37, pp. 63 - 76, January 2002.

    ABSTRACT:

    Lookahead signals to form the multilevel folding architecture for priority-encoding-based designs was used to improve the performance to the order of $O (\log N)$ . Analysis showed that both the multilevel lookahead and the multilevel folding techniques could be easily merged and implemented in the dynamic CMOS circuits. For the 256-bit priority encoder, the new design adopting all the proposed techniques can achieve nearly ten times performance while spending nearly half the power consumption as compared to the conventional design, utilizing only a simple lookahead structure. For the 64-bit incrementer/decrementer, the new design adopting all the proposed techniques requires less than one-third delay time as compared to a high-speed carry-select adder (CSA)-based incrementer/decrementer. The power consumption evaluated at the maximum operating frequency and the transistor count of the new incrementer/decrementer are also reduced to 67% and 35%, respectively, as compared to the CSA-based design. The measurement results indicate that the proposed 256-bit priority encoder and the proposed 64-bit incrementer/decrementer can operate up to 116 and 139 MHz, respectively, when they are designed based on a 0.6-\mum CMOS technology.

    REFERENCES:

    [1] D. H. Summerville, J. G. Delgado-Frias, S. Vassiliadis; A flexible bit-pattern associative router for interconnection networks, IEEE Trans. Parallel Distrib. Syst., vol. 7, pp. 477 - 485, May 1996.

    [2] Hiroshi Kadota, Jiro Miyake, Yoshito Nishimichi, Hitoshi Kudoh, Keiichi Kagawa; An 8-kbit content-addressable and Reentrant memory, IEEE Journal of Solid-State Circuits, vol. 20, pp. 951 - 957, October 1985.

    [3] S. Furber; ARM System Architecture, Addison-Wesley, Reading, MA, 1997.

    [4] R. Hashemian; Highly parallel increment/decrement using CMOS technology, Proc. 33rd IEEE Midwest Symp. Circuit and Systems, vol. 2, pp. 866 - 869, 1991.

    [5] C.-H. Huang, J.-S. Wang, Y.-C. Huang; A high-speed CMOS incrementer/decrementer, Proc. IEEE Int. Symp. Circuit and Systems, vol. 4, pp. 88 - 91, May 2001.

    [6] José Delgado-Frias, Jabulani Nyathi; A high-performance encoder with priority lookahead, IEEE Trans. Circuit Syst. I, vol. CAS-47, pp. 1390 - 1393, September 2000.

    [7] Jinn-Shyan Wang, Chung-Hsun Huang; High-speed and low-power CMOS priority encoders, IEEE Journal of Solid-State Circuits, vol. 35, pp. 1511 - 1514, October 2000.

    [8] 0.6-$\mu$m CMOS ASIC Process Dig., Taiwan Semiconductor Manufacturing Corporation, 1996.

    [9] N. West, K. Eshraghian; Principles of CMOS VLSI Design, Addison-Wesley, Reading, MA, ch. 8, 1993.

    9 downloads

    Submitted

  8. Physics-based closed-form inductance expression for compact modeling of integrated spiral inductors

    Physics-based closed-form inductance expression for compact modeling of integrated spiral inductors

    ISSUE: IEEE Journal of Solid-State Circuits, vol. 37, pp. 77 - 80, January 2002

    AUTHORS: Snezana Jenei, Bart K. J. C. Nauwelaers, and Stefaan Decoutere

    KEYWORDS: Inductance; Inductors; Inductors and transformers

    BIBLIOGRAPHIC ENTRY:
    S. Jenei, B. K. J. C. Nauwelaers, and S. Decoutere, "Physics-based closed-form inductance expression for compact modeling of integrated spiral inductors," IEEE Journal of Solid-State Circuits, vol. 37, pp. 77 - 80, January 2002.

    ABSTRACT:

    A closed-form inductance expression for compact modeling of integrated inductors is presented. The expression is more accurate than previously published closed formulas. Moreover, due to its physics-based nature, it is scalable. That is demonstrated by comparison with the measured inductance for a complete set of inductors with different layout parameters.

    REFERENCES:

    [1] Y. Koutsoyannopoulos, et al.; A generic CAD model for arbitrary shaped and multilayer integrated inductors on silicon substrates, Proc. ESSDERC, pp. 320 - 323, 1997.

    [2] John R. Long, M. Copeland; The modeling, characterization, and design of monolithic inductors for silicon RF IC's, IEEE Journal of Solid-State Circuits, vol. 32, pp. 357 - 369, March 1997.

    [3] Ali M. Niknejad, Robert G. Meyer; Analysis, design, and optimization of spiral inductors and transformers for Si RF ICs, IEEE Journal of Solid-State Circuits, vol. 33, pp. 1470 - 1481, October 1998.

    [4] H. M. Greenhouse; Design of Planar Rectangular Microelectronic Inductors, IEEE Trans. Parts, Hybrids, and Pack., vol. PHP-10, pp. 101 - 109, June 1974.

    [5] F. W. Grover; Inductance Calculations, Dover, New York, 1946.

    [6] Jan Crols, Peter Kinget, Jan Craninckx, Michiel Steyaert; An analytical model of planar inductors on lowly doped Silicon substrates for high frequency analog design up to 3 GHz, Symp. VLSI Circuits Dig. 10, pp. 28 - 29, June 1996.

    [7] Sunderarajan S. Mohan, Maria del Mar Hershenson, Stephen P. Boyd, Thomas H. Lee; Simple accurate expressions for planar spiral inductances, IEEE Journal of Solid-State Circuits, vol. 34, pp. 1419 - 1424, October 1999.

    14 downloads

    Submitted

  9. A CMOS bandgap reference without resistors by Arne E. Buck, Charles L. McDonald, Stephen H. Lewis, and T. R. Viswanathan

    A CMOS bandgap reference without resistors


    ISSUE: IEEE Journal of Solid-State Circuits, vol. 37, pp. 81 - 83, January 2002

    AUTHORS: Arne E. Buck, Charles L. McDonald, Stephen H. Lewis, and T. R. Viswanathan

    KEYWORDS: CMOS analog integrated circuits; CMOS integrated circuits; Energy gap; Reference circuits

    BIBLIOGRAPHIC ENTRY:
    A. E. Buck, C. L. McDonald, S. H. Lewis, and T. R. Viswanathan, "A CMOS bandgap reference without resistors," IEEE Journal of Solid-State Circuits, vol. 37, pp. 81 - 83, January 2002.

    ABSTRACT:

    This paper describes a bandgap reference fabricated in a 0.5-\mum digital CMOS technology without resistors. The circuit uses ratioed transistors biased in strong inversion together with the inverse-function technique to produce a temperature-insensitive gain applied to the proportional to absolute temperature (PTAT) term in the reference. After trimming, the peak-to-peak output voltage change is 9.4 mV from 0 $^{\circ}$ C to 70 $^{\circ}$ C. It occupies 0.4mm $^2$ and dissipates 1.4 mW from a 3.7-V supply.

    REFERENCES:


    [1] Robert J. Widlar; New Developments in IC Voltage Regulators, IEEE Journal of Solid-State Circuits, vol. 6, pp. 2 - 7, February 1971.

    [2] A. Paul Brokaw; A simple three-terminal IC bandgap reference, IEEE Journal of Solid-State Circuits, vol. 9, pp. 388 - 393, December 1974.

    [3] Arne Buck, Charles McDonald, Stephen Lewis, T. R. Viswanathan; A CMOS bandgap reference without resistors, IEEE International Solid-State Circuits Conference, vol. XLIII, pp. 442 - 443, February 2000.

    [4] R. R. Torrance, T. R. Viswanathan, J. V. Hanson; CMOS voltage to current transducers, IEEE Trans. Circuit Syst., vol. CAS-32, pp. 1097 - 1104, November 1985.

    [5] P. R. Gray, R. G. Meyer; Analysis and Design of Analog Integrated Circuits, 3rd ed., Wiley, New York, p. 345, 352, 1993.

    [6] W. Liu; MOSFET Models for SPICE Simulation, Including BSIM3v3 and BSIM4, Wiley, New York, p. 102, 2001.

    13 downloads

    Submitted

  10. Circuit techniques for a 1.8-V-only NAND flash memory

    Circuit techniques for a 1.8-V-only NAND flash memory

    ISSUE: IEEE Journal of Solid-State Circuits, vol. 37, pp. 84 - 89, January 2002

    AUTHORS: Toru Tanzawa, Tomoharu Tanaka, Ken Takeuchi, and Hiroshi Nakamura

    KEYWORDS: CMOS memory circuits; CMOS memory integrated circuits; Flash memories; Isolation technology; Low-power electronics; Memory circuits; NAND circuits

    BIBLIOGRAPHIC ENTRY:
    T. Tanzawa, T. Tanaka, K. Takeuchi, and H. Nakamura, "Circuit techniques for a 1.8-V-only NAND flash memory," IEEE Journal of Solid-State Circuits, vol. 37, pp. 84 - 89, January 2002.

    ABSTRACT:

    Focusing on internal high-voltage (Vpp) switching and generation for low-voltage NAND flash memories, this paper describes a Vpp switch, row decoder, and charge-pump circuit. The proposed nMOS Vpp switch is composed of only intrinsic high-voltage transistors without channel implantation, which realizes both reduction of the minimum operating voltage and elimination of the Vpp leakage current. The proposed row decoder scheme is described in which all blocks are in selected state in standby so as to prevent standby current from flowing through the proposed Vpp switches in the row decoder. A merged charge-pump scheme generates a plurality of voltage levels with an individually optimized efficiency, which reduces circuit area in comparison with the conventional scheme that requires a separate charge-pump circuit for each voltage level. The proposed circuits were implemented on an experimental NAND flash memory. The charge pump and Vpp switch successfully operated at a supply voltage of 1.8 V with a standby current of 10 \mu A. The proposed pump scheme reduced the area required for charge-pump circuits by 40%.

    REFERENCES:

    [1] F. Masuoka, M. Asano, H. Iwahashi, T. Komuro, S. Tanaka; A new Flash EEPROM cell using triple polysilicon technology, IEDM Tech. Dig., pp. 464 - 467, Dec. 1984.

    [2] Kenichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Toshihiko Himeno, Ken Takeuchi, Tamio Ikehashi, Kazushige Kanda, Koji Hosono, Riichiro Shirota, Seiichi Aritome, Kazuhiro Shimizu, Kazuo Hatakeyama, Koji Sakui; A 130mm2256 Mb NAND flash with shallow trench isolation technology, IEEE International Solid-State Circuits Conference, vol. XLII, pp. 112 - 113, February 1999.

    [3] Taehee Cho, Young-Taek Lee, Euncheol Kim, Jinwook Lee, Sunmi Choi, Seungjae Lee, Dong-Hwan Kim, Wook-Kee Han, Young-Ho Lim, Jae-Duk Lee, Jung-Dal Choi, Kang-Deog Suh; A 3.3V 1Gb multi-level NAND flash memory with non-uniform threshold voltage distribution, IEEE International Solid-State Circuits Conference, vol. XLIV, pp. 28 - 29, February 2001.

    [4] Shigeru Atsumi, Akira Umezawa, Toru Tanzawa, Tadayuki Taura, Hitoshi Shiga, Yoshinori Takano, Takeshi Miyaba, Michiharu Matsui, Hiroshi Watanabe, Kazuaki Isobe, Shota Kitamura, Seiji Yamada, Masanobu Saito, Seiichi Mori, Toshiharu Watanabe; A channel-erasing 1.8V-only32 Mb NOR flash EEPROM with a bit-line direct-sensing scheme, IEEE International Solid-State Circuits Conference, vol. XLIII, pp. 276 - 277, February 2000.

    [5] B. Pathak, A. Cabrera, G. Christensen, A. Darwish, M. Goldman, R. Haque, J. Jorgensen, R. Kajley, T. Ly, F. Marvin, S. Monasa, Q. Nguyen, D. Pierce, A. Sendrowski, I. Sharif, H. Shimoyoshi, A. Smidt, R. Sundaram, M. Taub, W. Tran, R. Trivedi, P. Walimbe, E. Yu; A 1.8V 64Mb 100MHz flexible read while write flash memory, IEEE International Solid-State Circuits Conference, vol. XLIV, pp. 32 - 33, February 2001.

    [6] Toru Tanzawa, Yoshinori Takano, Tadayuki Taura, Shigeru Atsumi; Design of a sense circuit for low-voltage flash memories, IEEE Journal of Solid-State Circuits, vol. 35, pp. 1415 - 1421, October 2000.

    [7] Toru Tanzawa, Akira Umezawa, Masao Kuriyama, Tadayuki Taura, Hironori Banba, Takeshi Miyaba, Hitoshi Shiga, Yoshinori Takano, Shigeru Atsumi; Wordline voltage generating system for low-power low-voltage flash memories, IEEE Journal of Solid-State Circuits, vol. 36, pp. 55 - 63, January 2001.

    [8] Ken Takeuchi, Shinji Satoh, Ken-ichi Imamiya, Koji Sakui; A source-line programming scheme for low-voltage operation NAND flash memories, IEEE Journal of Solid-State Circuits, vol. 35, pp. 672 - 681, May 2000.

    [9] John F. Dickson; On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique, IEEE Journal of Solid-State Circuits, vol. 11, pp. 374 - 378, June 1976.

    [10] Vinod K. Dham, Duane H. Oto, Keith H. Gudger, Geoffrey S. Congwer, Yaw W. Hu, Jay Olund, Sidney Nieh; A 5V-only E2PROM using 1.5µ lithography, IEEE International Solid-State Circuits Conference, vol. XXVI, pp. 166 - 167, February 1983.

    [11] Darrel D. Donaldson, Edward H. Honnigford, Louis J. Toth; +5V-only 32K EEPROM, IEEE International Solid-State Circuits Conference, vol. XXVI, pp. 168 - 169, February 1983.

    [12] Toru Tanzawa, Tomoharu Tanaka; A dynamic analysis of the Dickson charge pump circuit, IEEE Journal of Solid-State Circuits, vol. 32, pp. 1231 - 1240, August 1997.

    [13] Akira Umezawa, Shigeru Atsumi, Masao Kuriyama, Hironori Banba, Ken-ichi Imamiya, Kiyomi Naruke, Seiji Yamada, Etsushi Obi, Masamitsu Oshikiri, Tomoko Suzuki, Sumio Tanaka; A 5-V-only operation 0.6-µm flash EEPROM with row decoder scheme in triple-well structure, IEEE Journal of Solid-State Circuits, vol. 27, pp. 1540 - 1546, November 1992.

    [14] S. Aritome, S. Satoh, T. Maruyama, H. Watanabe, S. Shuto, G. J. Hemink, R. Shirota, S. Watanabe, F. Masuoka; A 0.67 $\mu$m $^2$ self-aligned shallow trench isolation cell (SA-STI) for 3 V-only 256 Mbit NAND EEPROMs, IEDM Tech. Dig., pp. 61 - 64, 1994.

    24 downloads

    Submitted

  11. Low-power high-performance arithmetic circuits and architectures

    Low-power high-performance arithmetic circuits and architectures


    ISSUE: IEEE Journal of Solid-State Circuits, vol. 37, pp. 90 - 94, January 2002

    AUTHORS: Amr M. Fahim and Mohamed I. Elmasry

    KEYWORDS: Adders; Carry logic; Circuit simulations; CMOS logic circuits; Integrated circuit design; Integrated circuit testing; Logic circuits; Logic design; Logic simulation; Logic testing; Low-power electronics; Multiplying circuits

    BIBLIOGRAPHIC ENTRY:
    A. M. Fahim and M. I. Elmasry, "Low-power high-performance arithmetic circuits and architectures," IEEE Journal of Solid-State Circuits, vol. 37, pp. 90 - 94, January 2002.

    ABSTRACT:

    A new class of dynamic differential logic families, swing limited logic (SLL), is proposed for low-power high-performance applications. Two implementations of SLL, short-circuit current logic (SC $^{2}$ L) and clock-pulse controlled logic (CPCL), are designed. Low power is achieved by aggressively reducing logic swing. Using a 0.35-\mum CMOS technology and a nominal supply voltage of 3.3V, an SC $^{2}$ L 8-bit carry ripple adder (CRA) is implemented. It offers an order of magnitude less energy-delay product than several other logic families. Furthermore, two multipliers are constructed to demonstrate how SLL can be used in large circuit applications.

    REFERENCES:

    [1] R. Gu, K. Sharaf, M. I. Elmasry; High-Performance Digital VLSI Circuit Design, Kluwer, Boston, MA, 1996.

    [2] B. G. Streetman; Solid State Electronic Devices, Prentice-Hall, Englewood Cliffs, NJ, 1995.

    [3] A. Fahim, M. Elmasry; SC$^{2}$L: A low-power high-performance dynamic differential logic family, IEEE Int. Symp. Low Power Electronics Design, pp. 88 - 90, 1999.

    [4] Pius Ng, Poras T. Balsara, Don Steiss; Performance of CMOS differential circuits, IEEE Journal of Solid-State Circuits, vol. 31, pp. 841 - 846, June 1996.

    [5] K. Hwang; Computer Arithmetic: Principles, Architecture, and Design, Wiley, New York, 1979.

    [6] A. D. Booth; A signed binary multiplication technique, Quart. J. Mech. Appl. Math., pt. 2, no. 4, 1951.

    [7] N. Weste, K. Eshraghian; Principles of CMOS VLSI Design, Addison-Wesley, Reading, MA, 1993.

    16 downloads

    Submitted

  12. Fast compensative design approach for the approximate squaring function

    Fast compensative design approach for the approximate squaring function


    ISSUE: IEEE Journal of Solid-State Circuits, vol. 37, pp. 95 - 97, January 2002

    AUTHORS: Ming-Hwa Sheu and Su-Hon Lin

    KEYWORDS: CMOS logic circuits; Combinational circuits; Error analysis; Integrated circuit design; Integrated circuit testing; Logic design; Logic testing

    BIBLIOGRAPHIC ENTRY:
    M. Sheu and S. Lin, "Fast compensative design approach for the approximate squaring function," IEEE Journal of Solid-State Circuits, vol. 37, pp. 95 - 97, January 2002.

    ABSTRACT:

    In this paper, a systematic compensation approach is presented to efficiently design the approximate squaring function with a simple combinational logic circuit. Also, a set of recursive Boolean equations for general outputs is derived such that the logic circuit can be rapidly designed and reused for various bit-width inputs. In logic implementation, our design approach possesses less circuit cost and lower critical delay. Moreover, in error analysis, the maximum relative error (MRE) and average relative error (ARE) of squaring approximation are significantly improved by at least 26.95% and 61.59%, respectively, as compared with the existing approaches. Finally, a 7-bit approximate squaring function chip is accomplished to verify the circuit performance based on 0.6-\mum CMOS technology. The chip layout occupies $127 \times 135\;\mu$ m $^{2}$ and the total number of transistors is 186.

    REFERENCES:
    The links below are references to articles within the collection. Please refer to the paper itself for a full list of references.

    [2] Mohammad R. Soleymani, Salvatore D. Morgera; A Fast MMSE Encoding Technique for Vector Quantization, IEEE Trans. Communications, vol. COM-37, pp. 656 - 659, June 1989.

    [3] Y. Ephraim; Statistical-model-based speech enhancement systems, Proc. IEEE, vol. 80, no. 10, pp. 152 - 155, Oct. 1992.

    [4] K. Hwang; Computer Arithmetic: Principle, Architecture, and Design, Wiley, New York, 1979.

    [5] M. Shammanna, S. Whitaker, J. Canaris; Cellular logic array for computation of squares, 3rd NASA Symp. on VLSI Design, pp. 2.4.1 - 2.4.7, 1991.

    [6] Aria Eshraghi, Terri S. Fiez, Kel D. Winters, Thomas R. Fischer; Design of a new squaring function for the Viterbi algorithm, IEEE Journal of Solid-State Circuits, vol. 29, pp. 1102 - 1107, September 1994.

    [7] Ahmed A. Hiasat, Hoda S. Abdel-Aty-Zohdy; Combinational logic approach for implementing an improved approximate squaring function, IEEE Journal of Solid-State Circuits, vol. 34, pp. 236 - 240, February 1999.

    13 downloads

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